Semiconductor apparatus and an improved structure for power lines

ABSTRACT

A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean application number 10-2013-0167003, filed on Dec. 30, 2013, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

Various embodiments relate to a semiconductor apparatus, and moreparticularly, to a semiconductor apparatus which can efficiently lay outpower lines electrically coupled to power supply pads.

BACKGROUND

A semiconductor apparatus continuously trends toward high degree ofintegration, high capacity and high speed operation. In particular,various efforts have been made to realize a semiconductor apparatus ofhigh performance within a limited area.

For example, as a semiconductor apparatus trends toward highperformance, an increasing number of power lines are needed. As thenumber of power lines increases in this way, a structure for efficientlylaying out the power lines is demanded.

SUMMARY

In an embodiment, a semiconductor apparatus may include: a first powersupply pad configured to supply a first power; a second power supply padconfigured to supply a second power; a first power line configured to bedirectly electrically coupled to the first power supply pad; and asecond power line configured to be directly electrically coupled to thesecond power supply pad.

In an embodiment, a semiconductor apparatus may include: one or more padrows including one or more first power supply pads and one or moresecond power supply pads; a first power line laid out on one side of thepad rows in a direction perpendicular an the extending direction of thepad rows, and directly electrically coupled to the first power supplypads; and a second power line laid out on an other side of the pad rowsin the direction perpendicular to the extending direction of the padrows, and directly electrically coupled to the second power supply pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a semiconductor apparatus inaccordance with an embodiment;

FIG. 2 is a configuration diagram of bonding pads in the semiconductorapparatus shown in FIG. 1;

FIG. 3 is a diagram explaining the layout structure of power supply padsand power lines in a semiconductor apparatus in accordance with anembodiment;

FIG. 4 is a diagram explaining the layout structure of power supply padsand power lines in a semiconductor apparatus in accordance with anembodiment;

FIG. 5 is a diagram explaining the layout structure of power supply padsand power lines in a semiconductor apparatus in accordance with anembodiment.

DETAILED DESCRIPTION

Hereinafter, a semiconductor apparatus will be described below withreference to the accompanying drawings through various to embodiments.

Referring to FIG. 1, a semiconductor apparatus 10 in accordance with anembodiment includes a plurality of memory banks 110, 120, 130 and 140.The respective memory banks 110, 120, 130 and 140 are constituted by aplurality of cell mats which are arranged in a matrix type. Each cellmat includes a cell array region 1110, and driving circuit regions 1120,1130 and 1140 which surround the cell array region 1110.

A plurality of signal lines (not shown) and a plurality of power lines(not shown) may be laid out over the respective memory banks 110, 120,130 and 140. A plurality of signal lines may be laid out over the cellarray region 1110, and a plurality of power lines may be laid out overthe driving circuit regions 1120, 1130 and 1140.

The driving circuit regions 1120, 1130 and 1140 may include senseamplifier blocks 1120 which are laid out adjacent to a pair of facingedges of the cell array region 1110; and sub word line driving blocks1130 which are laid out adjacent to a pair of facing edges of the cellarray region 1110 in a direction perpendicular to a direction in whichthe sense amplifier blocks 1120 are laid out.

The semiconductor apparatus 10 in accordance with an embodiment furtherincludes a peripheral circuit region 150 which is laid out between theplurality of memory banks 110, 120, 130 and 140. An address/commandprocessing unit (not shown), a data input/output processing unit (notshown), a voltage supply unit (not shown), and so forth are laid out inthe peripheral circuit region 150. Further, bonding pads (not shown),probing pads (not shown), and so forth may be laid out in the peripheralcircuit region 150.

As shown in FIG. 2, the bonding pads include clock input pads CLK,command input pads CMD, address input pads Address, data strobe padsDQS, data input/output pads DQ, reference voltage pads VREF for inputbuffers, and a power supply pad array 1500.

The power supply pad array 1500 may be laid out in the peripheralcircuit region 150 in such a way as to include one or more row of pads.

The power supply pad array 1500 plays the role of supplying power to thecircuits of the semiconductor apparatus, and may include a first powersupply pad POWER 1510 for supplying a first power and a second powersupply pad GND 1520 for supplying a second power.

Referring to FIG. 3, the first power supply pad POWER 1510 may includepower supply voltage pads 1511 (hereinafter, referred to as VDD pads1511) which may be laid out in a first pad row 1500A and power supplyvoltage pads 1513 dedicated for output drivers (hereinafter, referred toas VDDQ pads 1513) which may be laid out in a second pad row 1500B.

The second power supply pad GND 1520 may include ground voltage pads1521 (hereinafter, referred to as VSS pads 1521) which may be laid outin the first pad row 1500A and ground voltage pads 1523 dedicated foroutput drivers (hereinafter, referred to as VSSQ pads 1523) which may belaid out in the second pad row 1500B.

The power supply pad array 1500 may include a first pad row 1500A, and asecond pad row 1500B which is separated from the first pad row 1500A ina first direction. The first direction refers to a direction that isperpendicular to the extending direction of the first pad row 1500A.

The first pad row 1500A may include a plurality of VDD pads 1511 and aplurality of VSS pads 1521. The plurality of VDD pads 1511 and theplurality of VSS pads 1521 may be laid out in a second direction. Thesecond direction refers to the extending direction of the first pad row1500A.

The second pad row 1500B may include a plurality of VDDQ pads 1513 and aplurality of VSSQ pads 1523. The plurality of VDDQ pads 1513 and theplurality of VSSQ pads 1523 may be laid out in the second direction.

That is to say, each pad row may include both the first power supply pad1510 and the second power supply pad 1520.

Power lines for supplying power to various kinds of circuits (not shown)of the semiconductor apparatus may be electrically coupled to the powersupply pad array 1500. The power lines may include first power lines1610 which are directly electrically coupled to the first power supplypad 1510, and second power lines 1620 which are directly electricallycoupled to the second power supply pad 1520. The first power lines 1610may be laid out on one side of the pad row 1500A in a directionperpendicular to an extending direction of the pad row 1500A. The secondpower lines 1620 may be laid out on the other side of the pad row 1500Bin the direction perpendicular to the extending direction of the pad row1500B.

The first power lines 1610 may include a power supply voltage power line1611 (hereinafter, referred to as a VDD power line 1611) which isdirectly electrically coupled to the VDD pads 1511; and a power supplyvoltage power line 1613 dedicated for output drivers (hereinafter,referred to as a VDDQ power line 1613) which is directly electricallycoupled to the VDDQ pads 1513 that may be dedicated for an outputdriver. The VDD power line 1611 and the VDDQ power line 1613 may extendin the second direction.

The second power lines 1620 may include a ground voltage power line 1621(hereinafter, referred to as a VSS power line 1621) which is directlyelectrically coupled to the VSS pads 1521; and a ground voltage powerline 1623 dedicated for output drivers (hereinafter, referred to as aVSSQ power line 1623) which is directly electrically coupled to the VSSQpads 1523 that may be dedicated for an output driver. The VSS power line1621 and the VSSQ power line 1623 may extend in the second direction.The VSS power line 1621 may be laid out on the other side or the oneside of the first pad row 1500A in the direction perpendicular to theextending direction of the first pad row 1500A. The VSSQ power line 1623may be laid out on the other side or the one side of the second pad rowin the direction perpendicular to the extending direction of the secondpad row 1500B.

For example, the VDD power line 1611, which is directly electricallycoupled to the VDD pads 1511, may be laid out on one side or an otherside of the first pad row 1500A in the first direction; and the VSSpower line 1621, which is directly electrically coupled to the VSS pads1521, may be laid out on the other side of the first pad row 1500A inthe first direction.

The VSSQ power line 1623, which is directly electrically coupled to theVSSQ pads 1523, may be laid out on one side of the second pad row 1500Bin the first direction; and the VDDQ power line 1613, which is directlyelectrically coupled to the VDDQ pads 1513, may be laid out on one sideor the other side of the second pad row 1500B in the first direction.

In other words, in the semiconductor apparatus, the first power lines1610, which are directly electrically coupled to the first power supplypad 1510, may be laid out on the outer sides of the pad rows 1500A and1500B which include the first power supply pad 1510 and the second powersupply pad 1520; and the second power lines 1620, which are directlyelectrically coupled to the second power supply pad 1520, may be laidout on the inner sides of the pad rows 1500A and 1500B.

According to this fact, since the first power lines 1610 and the secondpower lines 1620 are directly electrically coupled to the pad rows 1500Aand 1500B, it is possible to stably supply the first power and thesecond power to the various kinds of circuits of the semiconductorapparatus.

A semiconductor apparatus in accordance with an embodiment will bedescribed below with reference to FIGS. 2 and 4.

A power supply pad array 1500 of the semiconductor apparatus may includea first power supply pad 1510 and a second power supply pad 1520. Sincethe power supply pad array 1500 is configured in the same manner as thepower supply pad array 1500 of the aforementioned embodiment above,detailed descriptions thereof will be omitted herein.

Power lines for supplying power to various kinds of circuits (not shown)of the semiconductor apparatus may be electrically coupled to the powersupply pad array 1500. The power lines may include first power lines1610 directly electrically coupled to the first power supply pad 1510;second power lines 1620 directly electrically coupled to the secondpower supply pad 1520; first auxiliary power lines 1630 indirectlyelectrically coupled to the first power supply pad 1510; and secondauxiliary power lines 1640 indirectly electrically coupled to the secondpower supply pad 1520. The first power lines 1610 may be laid out abovethe first and second pad rows 1500A and 1500B and the first auxiliarypower lines 1630. The second power lines 1620 may be laid out betweenthe pad row 1500A and the second power auxiliary power lines 1640. Thefirst auxiliary power lines 1630 may be laid out on one side or theother side of the pad row 1500A in the direction perpendicular to theextending direction of the pad row 1500A. The second auxiliary powerlines 1640 may be laid out on the other side or the one side of the padrow 1500B in the direction perpendicular to the extending direction ofthe pad row 1500B.

The first power lines 1610 may include a VDD power line 1611 directlyelectrically coupled to VDD pads 1511, and a VDDQ power line 1613directly electrically coupled to VDDQ pads 1513.

The second power lines 1620 may include a VSS power line 1621 directlyelectrically coupled to VSS pads 1521, and a VSSQ power line 1623directly electrically coupled to VSSQ pads 1523.

The first auxiliary power lines 1630 may include a power supply voltageauxiliary power line 1631 that may be dedicated for an output driver(hereinafter, referred to as a VDD auxiliary power line 1631) indirectlyelectrically coupled to the VDD pads 1511; and a power supply voltageauxiliary power line 1633 dedicated for output drivers (hereinafter,referred to as a VDDQ auxiliary power line 1633) indirectly electricallycoupled to the VDDQ pads 1513.

The first auxiliary power lines 1630 and pad row are laid out on thesame layer as the first power lines 1610 and at positions separated fromthe first power lines 1610 in the first direction. The first auxiliarypower lines 1630 may be electrically coupled to the first power supplypad 1510 through first coupling lines 1651 which extend in the firstdirection.

The first coupling lines 1651 are laid out on a layer different from thefirst power supply pad 1510 and the first auxiliary power lines 1630(for example, on an underlying layer) and the first power lines 1610.The first power supply pad 1510 and the first coupling lines 1651 may beelectrically coupled to each other through contacts 1655A. Each pad ofthe pad row 1500B and the first auxiliary power line 1630 may beelectrically coupled to the first coupling lines 1651 through contacts1655A. The first auxiliary power lines 1630 and the first coupling lines1651 may be electrically coupled to each other through contacts 1655B.

The second auxiliary power lines 1640 may include a ground voltageauxiliary power line 1641 (hereinafter, referred to as a VSS auxiliarypower line 1641) indirectly electrically coupled to the VSS pads 1521;and a ground voltage auxiliary power line 1643 dedicated for outputdrivers (hereinafter, referred to as a VSSQ auxiliary power line 1643)indirectly electrically coupled to the VSSQ pads 1523. The VSS auxiliarypower line 1641 may be laid out on the other side or the one side of thefirst pad row 1500A in the direction perpendicular to the extendingdirection of the first pad row 1500A. The VSSQ auxiliary power line 1643may be laid out on the other side or the one side of the second pad row1500B in the direction perpendicular to the extending direction of thesecond pad row 1500B.

The second auxiliary power lines 1640 are laid out on the same layer asthe pad row 1500B and the second power lines 1620 and at positionsseparated from the second power lines 1620 in the first direction. Thesecond auxiliary power lines 1640 may be electrically coupled to thesecond power supply pad 1520 through second coupling lines 1653 whichextend in the first direction.

The second coupling lines 1653 are laid out on a layer different fromthe second power supply pad 1520 of the pad row 1500A, the second powerlines 1620 and the second auxiliary power lines 1640 (for example, on anunderlying layer). The second power supply pad 1520 and the secondcoupling lines 1653 may be electrically coupled to each other throughcontacts 1655C. Each pad of the pad row 1500B, the second auxiliarypower lines 1640 and the second coupling lines 1653 may be electricallycoupled to each other through contacts 1655D.

For example, the VDD power line 1611 directly electrically coupled tothe VDD pads 1511; and the VSS auxiliary power line 1641 indirectlyelectrically coupled to the VSS pads 1521 through the second couplinglines 1653, may be laid out on one side of a first pad row 1500A in thefirst direction. The VDD power line 1611 may be laid out at a positioncloser to the first pad row 1500A than the VSS auxiliary power line1641.

The VSS power line 1621, directly electrically coupled to the VSS pads1521; and the VDD auxiliary power line 1631 indirectly electricallycoupled to the VDD pads 1511 through the first coupling lines 1651, maybe laid out on one side or the other side of the first pad row 1500A inthe first direction. The VDD auxiliary power line 1631 may be indirectlyelectrically coupled to the VDDQ pads 1513. The VSS power line 1621 maybe laid out at a position closer to the first pad row 1500A than the VDDauxiliary power line 1631.

The VDD power line 1611 and the VSS power line 1621 may be laid out atsubstantially the same distance from the first pad row 1500A; and theVDD auxiliary power line 1631 and the VSS auxiliary power line 1641 maybe laid out at substantially the same distance from the first pad row1500A.

The VSSQ power line 1623 directly electrically coupled to the VSSQ pads1523; and the VDDQ auxiliary power line 1633 indirectly electricallycoupled to the VDDQ pads 1513 through the first coupling lines 1651, maybe laid out on one side or the other side of a second pad row 1500B inthe first direction. The VSSQ power line 1623 may be laid out at aposition closer to the second pad row 1500B than the VDDQ auxiliarypower line 1633.

The VDDQ power line 1613 directly electrically coupled to the VDDQ pads1513; and the VSSQ auxiliary power line 1643 indirectly electricallycoupled to the VSSQ pads 1523 through the second coupling lines 1653,may be laid out on the other side of the second pad row 1500B in thefirst direction. The VDDQ power line 1613 may be laid out at a positioncloser to the second pad row 1500B than the VSSQ auxiliary power line1643.

The VDDQ power line 1613 and the VSSQ power line 1623 may be laid out atsubstantially the same distance from the second pad row 1500B; and theVDDQ auxiliary power line 1633 and the VSSQ auxiliary power line 1643may be laid out at substantially the same distance from the second padrow 1500B.

In other words, the first power lines 1610 directly electrically coupledto the first power supply pad 1510 and the second auxiliary power lines1640 indirectly electrically coupled to the second power supply pad1520, may be laid out on the outer sides of the pad rows 1500A and1500B. The pad rows 1500A may include the first power supply pad 1510;the second power supply pad 1520; the second power lines 1620 which aredirectly electrically coupled to the second power supply pad 1520; andthe first auxiliary power lines 1630, which are indirectly electricallycoupled to the first power supply pad 1510 and may be laid out on theinner sides of the pad rows 1500A and 1500B.

In the above-described structure, the first and second power lines 1610and 1620 may be laid out at substantially the same distance from the padrows 1500A and 1500B; and the first and second auxiliary power lines1630 and 1640 may be laid out at substantially the same distance fromthe pad rows 1500A and 1500B.

According to this fact, since the first power lines 1610 and the secondpower lines 1620 are directly electrically coupled to the pad rows 1500Aand 1500B and laid out between the pad rows 1500A and 1500B and thefirst auxiliary power lines 1630 and the second auxiliary power lines1640 are indirectly electrically coupled to the pad rows 1500A and 1500Bas described above, it is possible to stably supply a first power and asecond power to the various kinds of circuits of the semiconductorapparatus.

A semiconductor apparatus in accordance with an embodiment will bedescribed below with reference to FIGS. 2 and 5.

A power supply pad array 1500 of the semiconductor apparatus may includea first power supply pad 1510 and a second power supply pad 1520. Sincethe power supply pad array 1500 is configured in the same manner as thepower supply pad array 1500 of the aforementioned embodiments, detaileddescriptions thereof will be omitted herein.

Power lines for supplying power to various kinds of circuits (not shown)of the semiconductor apparatus may be electrically coupled to the powersupply pad array 1500.

The power lines may include first power lines 2610 directly electricallycoupled to the first power supply pad 1510, and second power lines 2620indirectly electrically coupled to the second power supply pad 1520.

The first power lines 2610 may include VDD power lines 2611 and 2612which are directly electrically coupled to VDD pads 1511, and VDDQ powerlines 2613 and 2614 which are directly electrically coupled to VDDQ pads1513.

The VDD power lines 2611 and 2612 may include a first VDD power line2611 which is laid out on one side of a first pad row 1500A in the firstdirection, and a second VDD power line 2612 which is laid out on theother side of the first pad row 1500A in the first direction.

The VDDQ power lines 2613 and 2614 may include a first VDDQ power line2613 laid out on one side of a second pad row 1500B in the firstdirection; and a second VDDQ power line 2614 laid out on the other sideof the second pad row 1500B in the first direction.

The second power lines 2620 may include a VSS power line 2621 indirectlyelectrically coupled to VSS pads 1521 through first coupling lines 2631extending in the first direction; and a VSSQ power line 2623 indirectlyelectrically coupled to VSSQ pads 1523 through second coupling lines2633 extending in the first direction.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor apparatusdescribed herein should not be limited based on the describedembodiments. Rather, the semiconductor apparatus described herein shouldonly be limited in light of the claims that follow when taken inconjunction with the above description and accompanying drawings.

What is claimed is:
 1. A semiconductor apparatus comprising: a first power line arranged in a first direction; a second power line arranged to be parallel to the first power line; a first power supply pad arranged between the first power line and the second power line to be directly connected to the first power line, wherein an entire portion of the first power supply pad is arranged between the first power line and the second power line; and a second power supply pad arranged between the first power line and the second power line and directly connected to the second power line, wherein an entire portion of the second power supply pad is arranged between the first power line and the second power line; a first auxiliary power line arranged to be parallel to the first power line and electrically coupled with the first power supply pad; and a second auxiliary power line arranged to be parallel to the second power line and electrically coupled with the second power supply pad, wherein the first power supply pad and the second power supply pad are arranged in a line.
 2. The semiconductor apparatus according to claim 1, wherein the first power supply pad comprises: a power supply voltage pad and a power supply voltage pad dedicated for an output driver, and the first power line comprises: a first power supply voltage power line which is electrically coupled to the power supply voltage pad, and a second power supply voltage power line dedicated for an output driver, which is electrically coupled to the power supply voltage pad dedicated for an output driver.
 3. The semiconductor apparatus according to claim 1, wherein the second power supply pad comprises: a first ground voltage pad and a second ground voltage pad dedicated for an output driver, and wherein the second power line comprises: a first ground voltage power line which is electrically coupled to the first ground voltage pad, and a second ground voltage power line dedicated for an output driver, which is electrically coupled to the ground voltage pad dedicated for an output driver.
 4. A semiconductor apparatus comprising: one or more pad rows including one or more first power supply pads and one or more second power supply pads; a first power line configured on one side of the pad rows in a direction perpendicular to the extending direction of the pad rows, and electrically coupled to the first power supply pads, wherein an entire portion of the first power supply pads is arranged between the first power line and a second power line; the second power line configured on an other side of the pad rows in the direction perpendicular to the extending direction of the pad rows, and directly electrically coupled to the second power supply pads, wherein an entire portion of the second power supply pads is arranged between the first power line and the second power line; a first auxiliary power line arranged to be parallel to the first power line and adjacent to the first power line; and a second auxiliary power line arranged to be parallel to the second power line and adjacent to the second power line.
 5. The semiconductor apparatus according to claim 4, wherein the pad rows comprise: a first pad row and a second pad row separated from the first pad row in a direction perpendicular to an extending direction of the first pad row.
 6. The semiconductor apparatus according to claim 5, wherein the first power supply pads comprise: a power supply voltage pad configured in the first pad row, and a power supply voltage pad dedicated for an output driver, and configured in the second pad row, and wherein the first power line comprises: a first power supply voltage power line configured on one side or the other side of the first pad row in the direction perpendicular to the extending direction of the first pad row, and electrically coupled to the power supply voltage pad; and a second power supply voltage power line dedicated for the output driver, configured on one side or the other side of the second pad row in the direction perpendicular to the extending direction of the second pad row, and electrically coupled to the power supply voltage pad dedicated for an output driver.
 7. The semiconductor apparatus according to claim 6, wherein the first auxiliary power line comprises: a first power supply voltage auxiliary power line laid out on the one side or the other side of the first pad row in the direction perpendicular to the extending direction of the first pad row, and indirectly electrically coupled to the power supply voltage pad; and a second power supply voltage auxiliary power line dedicated for an output driver, configured on the one side or the other side of the second pad row in the direction perpendicular to the extending direction of the second pad row, and indirectly electrically coupled to the power supply voltage pad dedicated for the output driver.
 8. The semiconductor apparatus according to claim 7, wherein the first power line is configured above the pad row and the first auxiliary power line.
 9. The semiconductor apparatus according to claim 8, wherein each pad of the pad row and the first auxiliary power line are electrically coupled to a first coupling line.
 10. The semiconductor apparatus according to claim 9, wherein the pad row, the first power line and the first auxiliary power line are configured on substantially the same layer, and wherein the first coupling line is configured on a layer different from the pad row, the first power line and the first auxiliary power line.
 11. The semiconductor apparatus according to claim 5, wherein the second power supply pad comprises: a first ground voltage pad which is configured in the first pad row, and a second ground voltage pad dedicated for an output driver, which is configured in the second pad row, and wherein the second power line comprises: a first ground voltage power line configured on the other side or the one side of the first pad row in the direction perpendicular to the extending direction of the first pad row, and electrically coupled to the ground voltage pad; and a second ground voltage power line dedicated for the output driver, configured on the other side or the one side of the second pad row in the direction perpendicular to the extending direction of the second pad row, and electrically coupled to the ground voltage pad dedicated for an output driver.
 12. The semiconductor apparatus according to claim 11, wherein the second auxiliary power line comprises: a ground voltage auxiliary power line configured on the other side or the one side of the first pad row in the direction perpendicular to the extending direction of the first pad row, and indirectly electrically coupled to the ground voltage pad; and a ground voltage auxiliary power line dedicated for the output driver, configured on the other side or the one side of the second pad row in the direction perpendicular to the extending direction of the second pad row, and indirectly electrically coupled to the ground voltage pad dedicated for an output driver.
 13. The semiconductor apparatus according to claim 12, wherein the second power line is configured between the pad row and the second auxiliary power line.
 14. The semiconductor apparatus according to claim 13, wherein each pad of the pad row and the second auxiliary power line are electrically coupled to a second coupling line.
 15. The semiconductor apparatus according to claim 14, wherein the pad row, the second power line and the second auxiliary power line are configured on substantially the same layer, and wherein the second coupling line is configured on a layer different from the pad row, the second power line or the second auxiliary power line.
 16. The semiconductor apparatus according to claim 4, wherein the first power line and the second power line are configured at substantially the same distance from the pad row.
 17. The semiconductor apparatus according to claim 5, wherein the first auxiliary power line is indirectly electrically coupled to the first power supply pad of the pad row and the second auxiliary power line is indirectly electrically coupled to the second power supply pad of the pad row, and wherein the first auxiliary power line and the second auxiliary power line are configured at substantially the same distance from the pad row.
 18. The semiconductor apparatus according to claim 17, wherein the first power lines are configured on an outer side of the first pad row and the second pad row.
 19. The semiconductor apparatus according to claim 18, wherein the second power lines are configured on an inner side of the first pad row and the second pad row. 